Synopsys Synthesis Tutorial

Index:

1. Introduction
2. Preparation
3. Simulate
4. Analyze & Elaborate
5. Applying Constraints
6. Optimization
7. Inspection of Results
8. Save & Quit

• Design Analyzer- a GUI (Graphical User Interface)
• dc_shell - a command line interface

 

 

iview &

1. If you use the C shell, add the following to your .chsrc file :


source /usr/local/scripts/setup.synopsys.csh

Remember to execute

$ source .cshrc
If you use the Bourne shell, add the following to your .profile file :

setup synopsys

Remember to execute

$ . .profile

2. Prepare a HDL (either in Verilog or VHDL) design. It is better to partition the design to speed up optimization run times, so that each block contains about 250 to 5000 gates.
3. As an example, say your design's name is "mychip", do the following steps :-
mkdir mychip
cd mychip
mkdir work
mkdir src
mkdir db
 
 
4. Create a file named .synopsys_dc.setup (use exactly the same name), this is the Design Compiler setup file, which is read and executed in the following location and order :-
• 1st : $SYNOPSYS/admin/setup directory
• 2nd : user's home directory and then
• 3rd : user's current working directory

 

 

A sample of mychip/.synopsys_dc.setup file looks like the following:
designer = "Mr. Tiny Chips"
company = "Less is More, Inc."
search_path = search_path + "./src" + "./db"
link_library = {"*", "class.db"}
target_library = "class.db"
symbol_library = "class.sdb"
define_design_lib WORK -path ./work
      Where:
• The default search_path is everything between double quotes "{".", "/opt/synopsys-3.5a/libraries/syn"}", this tells the Design Compiler to search for files or db at the current directory and at the libraries/syn directory where all the vendor libraries sources and db are placed. Instead of using class.db as your library, you can navigate to that libraries/syn directory, choose your preferred technology library and replace the above library assignment.

 

 

• The link_library is used to define any technology input to the synthesis process, the "*" is necessary as it tells the Design Compiler to search for the existing databases in the Design Compiler memory first.

 

 

• The target_library is the technology library to which you map your design during optimization.

 

 

• The symbol_library contains graphical data used to draw the symbols for the cells of the target or link libraries.
• A design library is a logical name referring to a UNIX directory which will store the intermediate files (the .mra .sim ... files) produced by analyze so as to not clutter up your present directory. You can choose other descriptive name besides work.
5. Copy the .synopsys_vss.setup file below and put it in your working directory (use exactly the same file name ).


           CY_CCPATH=/usr/bin/cc
         WORK > DEFAULT
         DEFAULT :

-- VHDL library to UNIX dir mappings --
SYNOPSYS : $SYNOPSYS/$ARCH/packages/synopsys/lib
IEEE  : $SYNOPSYS/$ARCH/packages/IEEE/lib
 
 
6. Place your HDL source files under the mychip/src directory

1. Verilog - you need to use cadence on HP workstation.

 

 

2. VHDL - Synopsys VHDL System Simulator (VSS) family of tools can analyze, simulate, and debug VHDL designs. You can either use VHDL Simulator or VHDL Debugger to simulate your design.

 

 

First you have to analyze all your soure files, including packages :-
vhdlan design_file
 
 
To run the simulation or debug the design in GUI :-
vhdldbx design &
 
 
The VHDL Debugger is invoked, you can select VHDL objects from source code displayed in a Text Viewer subwindow. Then, you can execute Simulator commands, for example, assigning values to VHDL objects, or display their current values. For more details, see Ch. 7 in the VSS Reference Manual, available on-line using iview.

To run the simulation in command line interface :-

• vhdlsim [Library.]Configuration_name

(if no design library name is specified, WORK would be used)
 
 
• The Simulator Prompt would appear, type run

 

 

• When a new prompt appear, type quit

 

 

1. To invoke Design Analyzer, enter the following at the directory mychip :


design_analyzer &

After the tool is finished initializing, the Design Analyzer window will pop up as shown in Fig. 1.
 
 



Fig. 1. The Design_analyzer with the Command Window opened

Note : the directory where you invoke design_analyzer would contain the command.log file which lists the commands executed.
2. Verify that your .synopsys_dc.setup file was executed by selecting Setup -> Defaults


Close the setup menu window by selecting Cancel, please DO NOT close any windows in the Design Analyzer by using the "close" window command of the native windowing environment! ALWAYS use the Cancel buttons provided.

3. Select Setup -> Command Window to bring up the window that gives you access to dc_shell and also immediate feedback on the progress of your synthesis session. Resize it and drag it to the appropriate place in your display. All commands entered via the menus of the Design Analyzer are echoed, so you can learn how to write dc_shell scripts later on.
4. Select File -> Analyze, double click on the src directory to see the appropriate files. Select the appropriate format for File Format, click on WORK in the Library box.

To analyze more than one HDL file: click on the first file with the left mouse button, and select the other files using the middle mouse button. Or simply type them all in the "File Name" box, separating the files with spaces (not commas).

The equivalent dc_shell command will be:

 $dc_shell>analyze -format verilog -lib WORK {"/entire_path_name/filename.v"}

 Note : The analyze command will do syntax checking and create intermediate .syn files which will be stored in the directory work, the defined design library. The elaborate command goes to the work directory to pick up the .syn files and builds the design up to the Design Compiler memory.

5. Inspect the messages in the Analyze window, correct any syntax errors in your HDL files and do the analyze again, otherwise, cancel the Analyze window and proceed.

 

 

6. Select File -> Elaborate, select WORK from the Library box, select your "top level design" from the Design box. Elaboration brings all the associated lower level blocks into the Design Compiler automatically (by following the dependency of the instantiations within the HDL code).


 After the elaboration is done, cancel the Elaborate window.

The equivalent dc_shell command will be:

 $dc_shell>elaborate module_name -arch "verilog" -lib WORK -update

 Instead of doing Analyze & Elaborate, you can also do just Read for a HDL design, the difference is that you have a choice of design library to place the analyzed design when you do Analyze, whereas with Read only the default library WORK is used.

Your design is now translated to a technology independent RTL model.
 
 

1. On the left side of the Design Analyzer window are the View buttons. The top 4 buttons select the type of view : Design, Symbol, Schematic or Text. The bottom 2 buttons are used to traverse the hierarchy of a design. Select the icon for your top level design block, say CONTROL, by clicking on it, the icon's border is shown as a dashed line instead of a solid line, the design is now CONTROL, as seen in the lower left corner of the Design Analyzer window.
2. Double click on the CONTROL icon and this will produce the Symbol View. The Symbol View is convenient for applying attributes and constraints to a design. Click on the appropriate port and select from the Attributes menu your desired constraints . If your design has a clock port, you have to select Dont Touch Network in the Specify Clock window, Synopsys does not effectively synthesize clock tree. Do not highlight a port if you want to create a virtual clock.

 

 

3. You can check for missing files by selecting from the main menu,


 Analysis -> Link Design

• The link command checks to make sure all parts in the current design are available in Design_Analyzer's memory.

 

 

• If there is a missing part ( also known as unresolved reference) you have to read in the file that contains the missing part.


 Note: If the missing part is saved as a .db file it is read in automatically during the execution of the link command.
 
 

The equivalent dc_shell command will be:

 $dc_shell> link

4. To check your design's netlist description for problems like connectivity, shorts, opens, multiple instantiations select,


Analysis -> Check Design

You can also check for potential timing problems (i.e. no clocks specified, outputs unconstrained for time) by clicking on Check Timing.

 The equivalent dc_shell command will be:

 $dc_shell>check_design
 
 

5. You may also select


Analysis -> Report -> Port

 and click on Timing Requirements to generate a report to verify port attributes and delay constraints.

The equivalent dc_shell command will be:

 $dc_shell>report_port
 
 

6. To set area constraint, select Attributes -> Optimization Constraints -> Design Constraints and set your desired Max Area. Note that the units of area, time, capacitance are defined by the vendor. To find out about the contents of a technology library, type the following commands in the command window :-


read library name.db
report_lib library name

where library name is the target library (without the '.db' extension).

 e.g:

 read class.db

report_lib class.
 
 

7. There is no menu option for set_driving_cell in Design Analyzer. Enter the command in the command window. It is in the following format :


set_driving_cell -library libname -cell cellname -pin pinname portlist.

• If no -library specified, default is the link library.
• -pin required only when the driving cell has more than 1 output pin.

 

 

Below is an example :-

set_driving_cell -cell "INV" all_inputs() - CLK

The inputs (except for the port CLK) are driven by the "INV" cell found in the link library.

8. At this point you may save your design as an unmapped db format, select File -> Save As, navigate to the ./db directory in the Directory menu, and name your design as control_unmap.db , choose DB as the File Format. When a design is saved as a .db file, the design plus all attributes are saved.


 The equivalent dc_shell command will be:

 $dc_shell>write -format db -hierarchy -output "/entire_path_name/module_name_unmap.db" {"/entire_path_name/module_name.db:module_name"}
 
 

9. Next time you want to retrieve the already elaborated but unmapped design, you could select File -> Read with DB as file format. You can enter reset_design in the command window to remove all attributes and apply new attributes if needed.

 

 

If your design contains hierarchy, it is recommended to use the Bottom-Up Hierarchical Compile approach (Note : in Synopsys, compile = synthesize = optimize). Compile sub-blocks independently, but do not compile the top level design.
1. Select Tools -> Design Optimization , the default Map Design setting is Medium. Then click on OK, it might take a few hours or even more than a day to compile. Do not apply other options in your first compile run.
2. When the optimization is complete, a Cancel button located at the bottom of the Compile window will become "grayed in" indicating that you can cancel the window and view your results.

 

 

1. Notice the changes in any icon of your design, it is now optimized to gate level, double click on the icon to reach the Symbol View, then click on the Schematic View button to inspect the design. Select View -> Zoom In or do &ltCtrl V> to zoom in.
2. You can select pin(s) or port(s) from the design, then select from Analysis -> Highlight a type of highlighting to see the path to the pin or port. &ltCtrl T> is a shortcut to highlight the critical path.
3. Select a design block (the top level design if your design is hierarchical), do Analysis -> Report, click on Area, Timing , you could direct the output to a file for later reference. Inspect the Report Output window, use the mouse to select a line, click on the Show button, the item(s) in the corresponding schematic will be "selected" automatically.


The equivalent dc_shell command will be:

 $dc_shell>report_area

 report_timing
 
 

4. Inspect the timing report, each Incr entry indicates the delay from the previous point to the current point, and the Path entry indicates the total delay from the input external delay to the current point. You can detect any suspicious path with exceptional long delay through this inspection. The most important thing is to check the slack, which is the required delay minus the actual delay , if it reports MET, your design has met the timing constraints, if it reports VIOLATED , you should go back to your HDL code and re-write it to improve timing. Then go back and re-analyze - elaborate the block and compile the whole design again.

 

 

1. Save your design by selecting File -> Save As, navigate to the .db directory in the Directory menu and choose DB as the File Format, it is recommended to use the Save All Designs in Hierarchy option.
2. You might want to read in another design without quitting Design Analyzer, you could first remove the current design by selecting the design to be removed, then Edit -> Delete . This would remove the design from the Design Compiler memory, it would not remove any physical design files.

 

 

3. To quit the Design Analyzer, select File -> Quit and click OK.