3. Inserting Scan
- For this tutorial, we will be doing partial scan. From the Design Analyzer
menu, select ATTRIBUTES > OPTIMIZATION CONSTRAINTS > DESIGN CONSTRAINTS.
Under test constraints, select the minimum fault coverage to be 80%.
When determining which elements to convert to scan, Synopsys will shoot
for 80% fault coverage. After setting the minimum fault coverage to 80%,
click on Apply.
Figure 14
- If the Test Synthesis window is not already open, from the Design Analyzer
menu select TOOLS > TEST SYNTHESIS. If you wish to do partial
scan, click on partial scan. If you wish to do full scan, click
on full scan. Next, click on Apply.
Figure 15
- Click on Insert Internal Scan Circuitry. You should see the window
shown in Figure 16. Click on OK.
Figure 16
- When the command has been completed, twp of the flip flops
should be converted to scan. Notice that on the other two flip flops were
not coverted to scan. In addition, an or gate, (highlighted by dashes in
the figure below,) has been added to the clock, disabling the clock during
testing. By doing this, the regular flip flops do not change value during
testing.
Figure 17
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