1. From the tools menu from the popup bar, select TOOLS > TEST SYNTHESIS
Make sure that Multiplexed Flip Flop is selected and click on the Check Design Rules button.

2. The Design Rules Errors should pop up. Click on the line  Warning: Shift clock pin CP of cell OUT_reg[3] (FD2) is illegally gated (TEST-186). The warning line should appear in black.
   
   
   
   Figure 9
   


3. Next, click on Show in the Design Rules Error window. In the design window, you should see the pin on the Flip Flop OUT[3], the FD2 component, which is highlighted in Figure 10. Notice that the clock input of FD2 is connected to a AND2P gate.
   
   
   
   Figure 10