1. Introduction
2. Checking the Design For Testability
3. Inserting Scan
4. Generating the Test Patterns

This tutorial covers the basics of using Synopsys Test Compiler. We will use a small design example that has one testability problem and fix it. The design that we will use is shown on the next page in Figure 1. As well as solving the testability problem in the design, we will use partial scan techniques for scan insertion. In addition, we will generate test vectors and measure test coverage. In order to go through this tutorial, you must have your .synopsys_dc.setup file set up properly. For further information on this, please see the Synopsys Design Compiler Tutorial. This tutorial will use Design_Analyzer so we graphically can look at the results. The dc_shell equivalent will also be displayed.

1. Enter the command Design_Analyzer & at the Unix prompt to start up Design Analyzer. To invoke dc_shell using the design compiler without the graphical interface, type dc_shell.
   
   
2. To read in the verilog file, select READ, from the top of the menu bar . Move to the directory that the Verilog file is in and select ud_counter2.v. Change the file format to Verilog as shown in Figure 2. Click on OK.
   
   
   
   Figure 2
   
   If you are using dc_shell, type the command read -f verilog ud_counter2.v
   
   
3. When done with reading the file, double click on the design icon in the middle of the design analyzer window. You should see the result shown in Figure 3.
   
   
   
   Figure 3
   
   
4. At the top of the menu, select the menu Attributes > Optimization Directives > Design. Under the Test Scan Style category, select Multiplexed Flip Flop and click on apply.
   
   
   
   Figure 4
   
   
5. Next, specify the clock for the design constraints. From the menu, pick Attributes > Clock. Change the clock period to 20 and then click on Apply.
   
   
   
   Figure 5