Flextest Command Line Interface






  1. Have your Verilog HDL design ready and go to step 4, or
  2. Copy the following files to that directory by entering the shell command:

  3.  

     

    shell > cp -R /applications/webserver/docs/mentortu/UD_COUNTER .
     

  4. Copy the attributes file by entering the following shell command.

  5.  

     

    shell> cp /applications/webserver/docs/mentortu/UD_COUNTER.mgc_component.attr .
     

  6. If you have do not already have a test library for the counter, a test library is listed at the end of this web page. Cut and paste the test library into a text file and save it as atglib. Make sure that you save it in the directory that you have your edif file in.

  7.  
  8. Make sure you are in the current directory that you have your edif file in. Set the mentor graphic working directory to your current directory by entering the following shell command.

  9.  

     

    shell > MGC_PWD=`pwd`
    shell > export MGC_PWD=`pwd`
     

    Note: Apostrophies surround pwd not single quotes.
     

  10. To invoke Flextest as a command line interface,enter:

  11.  

     

    shell> flextest UD_COUNTER -eddm -lib atglib -nogui -falcon
    shell> flextest <your-design>.v   -verilog -lib atglib -nogui -falcon
     

  12. To add clocks in the command line mode, enter the following command. The clocks are all inputs that directly affect the operation of the flip flops.

  13.  

     

    SETUP> add clocks 0 CLK RESET

  14. Specify the test cycle for you test patterns by entering the following command:

  15.  

     

    SETUP> set test cycle 2
     

  16. Add pin constraints by entering the following command:

  17.  

     

    SETUP> add pin constraints clk sr0 1 1 1
     

  18. To run rules checking, enter the following command.

  19.  

     

    SETUP> set system mode atpg
     

  20. This step is only needed if you plan on doing IDDQ testing, otherwise you may skip this step. Enter the following command:

  21.  

     

    ATPG> set fault type IDDQ

  22. To create an internal fault list, enter the command shown below.

  23.  

     

    ATPG> add faults -all

  24. To generate the test patterns, enter the following command:

  25.  

     

    ATPG> run

  26. To take a look at the coverage statistics, enter the following command:

  27.  

     

    ATPG> report statistics

    For a detailed explanation of the fault types, click here.
     

  28. To take a look at the Hypertrophic faults, enter the following command:

  29.  

     

    ATPG> report faults -Class Hyp -all

  30. To save the test patterns in ASCII format, enter the following command:

  31.  

     
     
     

    ATPG> save pattern ud_counter_ps.pats

    or if you wish to save them in verilog format, enter:

    ATPG> save patterns ud_counter_ps.pats -verilog

  1. To terminate the session, enter the following command:

  2.  

     

    ATPG> exit
     



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Test Library


 






model anotb (OUT, B, A) (

model aorbn (OUT, B, A) ( model dff (QBAR, Q, DATA, CLOCK) ( model dfsc (SCAN, QBAR, Q, DATA1, DATA, CLOCK) ( model dffr (RESET, QBAR, Q, DATA, CLOCK) ( model dfscr (SCAN, RESET, QBAR, Q, DATA1, DATA, CLOCK) ( model dffsr (SET, RESET, QBAR, Q, DATA, CLOCK) ( model dfscsr (SET, SCAN, RESET, QBAR, Q, DATA1, DATA0, CLOCK) ( model inv1 (OUT, IN1) ( model nd2x1 (OUT, IN2, IN1) ( model nd4 (OUT, IN4, IN3, IN2, IN1) ( model ndi2x1 (OUT2, OUT1, IN2, IN1) ( model nr3 (OUT, IN3, IN2, IN1) ( model xor (OUT, IN2, IN1) (

 
 


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