QuickLogic FPGA Auto Routing Tutorial

Savitha Gandikota

Samiha Mourad

Electrical Engineering Department

Note: For VHDL to QuickLogic FPGA please refer to the Mapping VHDL to QuickLogic FPGA Tutorial

Index:

1. Introduction
2. Preparation
3. Schematic Entry
4. Functional Simulation
5. Generate QuickLogic Netlist File (.edif)
6. Auto Routing and Results Examining
7. Importing EDIF
8. Timing Simulation

• In order to invoke QuickLogic libraries you will need to make following changes in your .profile or .cshrc files: (you can make these modifications using text editor --the third icon from the left at the bottom window of the work table).
  1. Add the following lines in your .profile :

     ./usr/local/scripts/setup.quicklogic.sh

     Remember to execute

     $ . .profile

  2. Add the following lines in your .cshrc :

     source/usr/local/scripts/setup.quicklogic.sh

     Remember to execute

     $ source .cshrc

     (Executing the .profile/.cshrc files is necessary only for the first time you changed the code in your file.)

  3. You shlould also have the .spderc file in home directory.

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  3. Schematic Entry

  1. Invoke 'Design Manager' by

     $ ql_dmgr

  2. Double click ql_da icon in the 'Tools' window and the 'Design Architect' window is generated.

     (You can also type in ql_da to invoke Design Architect with the QuickLogic libraries on the command line.)

  3. Select 'Open Sheet' from the 'Session Pallette' window. A dialog box will appear.

  4. In the box labelled "Component Name" complete the path with the name of the component you will be creating. Then click 'OK'.

  5. To enter your schematic, first select the 'QUICKLOGIC LIB' libraries by clicking the left mouse button on "Libraries" in the menu bar. Then click on 'QUICKLOGIC' library.

  6. A list of components will appear in the palette. Select the necessary components needed for your schematic, place them and route them.

     ( Please refer to the Design_Architect tutorial if you are not familiar with schematic entry. The tutorial also explains how to change the port names.)

  7. It is necessary to have input and output pads in your schematic. They can be selected by clicking on PAD from the 'QUICKLOGIC' library pallette.

     Note: The pad has to placed between the Input (Ouput) port and the input (Output) net.

  8. Then check and save your sheet.

  9. It is also necessary to Generate a Symbol for the schematic you entered. Make sure that your schematic does not have any errors before you generated the symbol.

  10. To Generate the Symbol from the main menu bar, select

      Miscellaneous -> Generate Symbol

      A new window opens. Click on OK to accept the default options.

  11. When the symbol sheet appears, add the property called DEVICE_TYPE and set its value equal to p8x12b . Also add the property called PACKAGE_TYPE and set its value to pl68 . Then click the OK button, and add both of these properties to the your top-level symbol.

  12. Check and save the symbol. You can minimize the Design Architect window.

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  4. Funtional Simulation

  1. In the Design Manager, invoke Quicksim II from the Tools window by double_clicking on ql_qsim .

  2. Select the design you created in the Design Architect using the Navigator button. For pre-layout simulaton, make sure the "Timing Mode" is set to "Unit". Then click on OK to launch the QuickSim II.

  3. Do the simulation like you have done before or see the appropriate tutorial on Quicksim.

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  5. Generate QuickLogic Netlist File (.edif)

  1. To translate your design into a QuickLogic Netlist File (.edif), from the Design Manager, double-click on ql_edifout . Use 'Navigator' to select your design. Also, specify a filename in the "Output netlist file" field.

     (Note: The Output netlist name has to be the same design name with extention edif. For example if your design name is 'fulladder' then the output netlist file name should be 'fulladder.edif').

  2. Then click on OK .

     Note: If you do not specify a pathname for the .edif filename it will be created in the $MGC_WD directory)

  3. Verify that the netlist has been generated successfully by checking the existance of the .edif file.

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  6. Auto Routing and Results Examining

  1. Invoke SpDE from the Mentor Graphics Design Manager by double-clicking its icon in the Tools window.

  2. A dialog box will prompt for a ".chp" file(a placed and routed design), or a ".edif" file. Use the Navigator to select the .edif file you created using ql_edifout . And then click OK to launch SpDE.

  3. Once the SpDE window appears, select Import -> EDIF from the File menu.

  4. Locate the EDIF file you exported for your schematic design and then click OK .

  5. From main menu select,
     View ->fit.

  6. Then run it by selecting from the main menu,
     Tools -> run tools and then clicking on OK

  7. Save (this step creates a .chp file).

  8. The physical view of the chip will be displayed (the internal array will be blank initially, because the design has not been mapped yet).

  9. For optimization,
     Tools -> path analyzer
     then enter the optimal time you need for a given net and Runtools and observe the change in the design.

  10. You can close the SpDE now.

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  7. Backannotation

  1. From the Mentor Graphics Design Manager, invoke the EDIF importer, ql_edifin , by double-clicking on its icon in the tools window.

  2. Specify the .edo file that SpDE has generated and make sure that the "Create" checkbox is selected under "Automatic Schematic Generation". Then click OK .

  3. A new EDDM database will be generated for post-layout simulation. A subdirectory called DESIGN is generated under which the design will be stored.

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  8. Timing Simulation

  1. Invoking the QuickSim is the same as earlier. Select the design under the DESIGN directory and make sure that Timing Mode is set to Constraint . And then click OK .

  2. Do the simulation as you have done earlier, (see Section 4 of this tutorial.)

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