2. Preparation
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Before running Quickfault II, you have to create a gate level design schematic.
In this tutorial, we are using the verilog design ud_counter.v. The file
is located in the directory /applications/webserver/docs/mentortu. Synthesize
your design with Autologic
by using CMOSN 1.2 micron worst Technology. After mapping your design
in Autologic, save your design as an Eddm netlist. For further information
on this part, please see the Autologic
tutorial.
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Create the Design viewpoint for your design. To invoke Design Viewpoint
enter the following command at the shell prompt.
$ cmosn_dve &
The dve window will open as shown in Figure 2.
Figure 2
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Select OPEN VPT from the setup palette and navigate to your design. If
you are having trouble finding your design. Go to the shell and type in
the Unix command
$ env | grep MGC_WD
This will tell you where your working directory is for Mentor Graphics.
Navigate to that directory and select UD_COUNTER.
Figure 3
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From the main menu bar, select SETUP> CMOSN SIMULATION. A popup
menu will appear as shown in Figure 4. Make sure that the Technology is
1.2 - Worst. and click OK.
Figure 4
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From the main menu bar, select SETUP > (QUICK)SIM, FAULT, PATH and GRADE.
Once this command has been completed, you should see something similar
to the window shown in Figure 5
Figure 5
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From the file menu, select FILE > SAVE DESIGN VIEWPOINT. You should
see the message Viewpoint default is saved at the bottom of the mentor
screen.
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Close the Design Viewpoint window.
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