6. Layout Extraction

6-1.Back Annotation For Post-Layout Simulation in Accusim & Layout Extraction for HSPICE netlist

After you make sure the layout complies with the design rules (DRC) and matches your schematic (LVS), you may want to "run" your layout in an analog simulator to see if it works, i.e. to run post-layout simulation. The parasitic devices which include net capacitance, net resistance and coupled capacitance create delays in your circuit. They can be back annotated to your schematic for a more realistic evaluation of circuit performance. To do this, follow the procedure given below.
 
 
  1. From 'IC Palettes', select "ICextract(M)"

  2.  

     

  3. Select 'Load Rules' to load the rules file. You may enter the rules filename or use Navigator to choose the rules file that you have created.

  4. In this example, enter "$MGC_CMOSN_LIB/physical_lib/cmosn.rules" for the rules file name then click on 'OK'.

  5. Open your logic (i.e. schematic) by selecting
  6. Logic -> open

    from ICextract(M) palette.

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