Mentor Graphics IC Verify Tutorial

Important:

Index:

1. Introduction
2. Preparation
3. Starting
4. Design Rule Check (DRC)
5. Layout VS. Schematic (LVS) Check
6. Layout Extraction
• 6-1.Back Annotation For Post-Layout Simulation in Accusim & Layout Extraction for HSPICE netlist

1. Design Rule Checking (DRC) : for physical design rules verification.

 

 
 
 
 
 
 
 
 
 

2. Layout Versus Schematic (LVS) : for checking if layout structure matches with original schematic design.

 

 
 
 
 
 
 
 
 
 

3. Layout Extraction : for getting the netlist from layout as well as unexpected parasitic resistance and capacitance.

 

 
 
 
 
 
 
 
 
 

The example we will be using in this tutorial is that of an inverter -- the same one created in ICgraph tutorial. The transistor schematic is shown in Fig 1-1 while its layout is shown in Fig 1-2. Please refer to ICgraph tutorial for basic editing skills whenever the layout needed to be modified.
 
 

• We recommend that you read the 'Design Rules' (page 1-1 to page 1-15) in the IC Station Menu (PostScript file).

PLEASE, DO NOT PRINT OUT THESE FILES !!!!!

• The rules are listed in a system text file "$MGC_CMOSN_LIB/physical_lib/cmosn.rules".

 

 
 
 
 
 
 
 
 
 

• Before using Mentor Graphics ICverify:

 

 
 
 
 
 
 
 
 
 

1. Add the following lines to your .profile file:

 

 
 
 
 
 
 
 

. /usr/local/scripts/setup.mentor-B.2.sh

SYNLIB=/LINKS/mentor/parts/cmosn_lib/autologic

 MGC_PLOT_DEFAULT_PRINTER=laser

export MGC_PLOT_DEFAULT_PRINTER

Remember to execute

 $ . .profile

2. If you are using C-shell add the following lines to your .cshrc file:

 

 
 
 
 
 
 
 

./usr/local/scripts/setup.mentor-B.2.csh

setenv SYNLIB /LINKS/mentor/parts/cmosn_lib/autologic

 setenv MGC_PLOT_DEFAULT_PRINTER laser

Remember to execute

 $ source .cshrc
 
 

Note: The above settings apply only to the SCU Design Center environment. Please consult with your system administrator for environment setting.

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3. Starting

1. Invoke 'IC Station' by

$ dmgr

2. Double click 'ic' icon in the 'Tools' window as shown in Fig 3-1 to invoke 'Ic Station'

 

 
 
 
 
 
 
 

Note:Don't forget to maximize 'Ic Station' window by clicking on the upper right button on the window frame when it appears otherwise a part of the palette will be hidden.

 Note:You can also invoke 'Ic Station' by typing 'ic' at the unix prompt.



 Figure 3-1. Double click 'ic' icon to invoke Ic Station
3. Select 'Open' on the right hand side session palette in the Ic Station window, a dialog box will appear. Enter the name of your layout or locate it directly using Navigator, then click on 'OK'.

 

 
 
 
 
 
 
 

 Your layout will appear in the window.
 
 

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4. Design Rule Check (DRC)

ICrules is the tool that provides Design Rule Checking (DRC) capability for ICgraph designs. The design rules we adopt in this example are the Lambda rules for 1.2 micron technology. In order to demonstrate how DRC works, we need to create one error on purpose in the layout. Say , we make the overlap of pwell over nplus-aa less than 6 Lambda as shown in Figure 4-1. (lower right corner of figure 4-1) .Then save it.
 
 



 Figure 4-1. Layout for Design Rule Check
1. Select 'ICrules' on the right side palette to switch to ICrules palette.
2. Select 'Load Rules' to load the rules file. You may enter the rules filename or use Navigator to choose the rules file have created.

 

 
 
 
 
 
 
 

For this example, enter "$MGC_CMOSN_LIB/physical_lib/cmosn.rules" for the rules file name, then click on 'OK'.



 Figure 4-2. Load design rules file
3. Select 'Check' on the palette. A display prompt bar appears at the bottom of the window. Click 'OK' or simply press return.

 

 
 
 
 
 
 
 
 
 

4. After running DRC, a message will appear at the bottom of the IC window. The term 'Total Result' means error. "Total results 0" means there are no errors and your layout is OK. In this example , "Total Result 1" should be read in that message.

 

 
 
 
 
 
 
 
 
 

5. Select 'First' in the "Set Scan To" division. The first error will blink and a message :



 Figure 4-3. Messages about first error will be shown at the bottom of the IC window.



 Figure 4-4. The first error is illustrated in bold white line If no error occur