Figure 4-15. Create input metal1

Figure 4-16. Connect input metal1 and Gate poly

  • Connect the drains of both transistors by metal1, to get output net of the inverter.

    Figure 4-17. Connect Drain to output port

    If you need to have well ties in layout-- continue with the following steps:

    1. Use 'Move Edge' (section 4.3 Modify shapes) to extend the well and aa(active area) length as shown in Fig 4-18.

      Figure 4-18. Extend the well and aa length

    2. Add nplus inside nwell and pplus inside pwell as shown in Fig 4-19.

      Figure 4-19. Add nplus inside nwell and pplus inside pwell

    3. Add metal1 and contact to both nplus and pplus and connect them to VCC and GND respectively.

      Figure 4-20. connect well tie to VCC and GND

      Notice that the PMOS's source is connected to VCC and NMOS's source is connected to the GND. By connecting the body of the wells to the sources through metal1 we are connecting the Nwell to VCC and Pwell to the GND.

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