Fastscan Command Line Interface


  1. Cut and paste the test library given at the bottom of this page into a text editor and call the file atglib. Make sure that you save it in the directory that the file ud_counter_fs.edif is in.
    Note: Before doing this tutorial, you must first generate an edif netlist using DFTADVISOR. See the DFTAdvisor tutorial.
  2. Set the mentor graphics working directory variable to the directory that your library is in.
    Enter the following shell command:

    shell> MGC_WD=`pwd`

    Note: Apostrophies surround pwd and not single quotes.

  3. To invoke Fastscan as a command line interface add the -nogui option as shown below:

    shell> fastscan ud_counter_fs.edif -edif -lib atglib -nogui

    If you wish, you may use the dofile generated by DFTAdvisor and skip steps 4, 5and 6. The dofile will add the clocks, the scan chain and the scan group.

    shell> fastscan ud_counter_fs.edif -edif -lib atglib -dofile ud_counter_fs.dofile



  4. Define the clocks for the scan circuitry, type in the commands shown below. The clocks are the inputs that directly affect the operation of the flip flops. Enter the commands shown below:


    SETUP> add clocks 0 CLK

    SETUP> add clocks 0 RESET
  5. Identify the scan group. The command below gives you the group name followed by the filename of the test procedure for the scan group.

    SETUP> add scan groups grp1 ud_counter_fs.testproc
  6. Identify the scan chain that you will use to scan the test vectors in and read the results from. Enter the following command:

    SETUP> add scan chains chain1 grp1 scan_in1 OUT(3)


  7. Set the system mode for automatic test pattern generation. This command will also do rule checking to make sure that the scan circuitry you have identified will function correctly.

    SETUP> setup system mode atpg
  8. If you wish to do IDDQ testing, enter the following command, otherwise skip this step:

    ATPG> set fault type IDDQ
  9. Add all the stuck at faults in the circuit. Enter the following command:

    ATPG> add faults -all

  10. Generate the test vectors by entering the following command:

    ATPG> run

  11. Check to see how much fault coverage that you received from the patterns. In addition this command will show you how many test vectors were generated.

    ATPG> report statistics

    For a detailed explanation of the fault types listed, click here.
  12. Next check and see which of the faults are untestable. Enter the following command.
    ATPG> report faults -Class UT -all

  13. Save the patterns in an ASCII file format by entering the following command:

    ATPG> save patterns ud_counter_fs.pats

    or if you wish to save them in verilog format, enter:

    ATPG> save patterns arbiter_fs.pats -verilog

  14. To terminate the session, at the popup command line, select:

    exit

    or, from the command line, enter:

    ATPG> exit



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Test Library

model anotb (OUT, B, A) (

model aorbn (OUT, B, A) (

model dff (QBAR, Q, DATA, CLOCK) (

model dfsc (SCAN, QBAR, Q, DATA1, DATA, CLOCK) (

model dffr (RESET, QBAR, Q, DATA, CLOCK) (

model dfscr (SCAN, RESET, QBAR, Q, DATA1, DATA, CLOCK) (

model dffsr (SET, RESET, QBAR, Q, DATA, CLOCK) (

model dfscsr (SET, SCAN, RESET, QBAR, Q, DATA1, DATA0, CLOCK) (

model inv1 (OUT, IN1) (

model nd2x1 (OUT, IN2, IN1) (

model nd4 (OUT, IN4, IN3, IN2, IN1) (

model ndi2x1 (OUT2, OUT1, IN2, IN1) (

model nr3 (OUT, IN3, IN2, IN1) (

model xor (OUT, IN2, IN1) (



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