Fastscan Graphical Interface
  1. Invoking Fastscan
  2. Adding the Clocks
  3. Identifying the Scan Circuitry
  4. Generating the Test Patterns
  5. Viewing and Saving the Results

1. Invoking Fastscan

  1. Fastscan requires a test library to identify the functions of all the parts in the design. Cut and paste the test library given at the bottom of this page into a text editor and save it as atglib.

  2. Make sure that you save it in the same directory that your design netlist is in.
  3. Set the mentor graphics working directory variable to the directory that your design netlist and test library are in. Make sure you are in the directory that your design netlist is in and enter the following shell command:

  4. shell> MGC_WD=`pwd`
    Note: apostrophies are surrounding the pwd and not single quotes.

  5. To invoke Fastscan from the shell prompt, enter:

  6. shell> fastscan {design_name} -v -verilog {library_name}

    For this example, enter:

    shell> fastscan ud_counter_fs.v -verilog -lib atglib
     

    After the command has completed execution, you should see the graphical interface shown below in Figure 1.


     

Figure 1


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Test Library

model anotb (OUT, B, A) (

model aorbn (OUT, B, A) ( model dff (QBAR, Q, DATA, CLOCK) ( model dfsc (SCAN, QBAR, Q, DATA1, DATA, CLOCK) ( model dffr (RESET, QBAR, Q, DATA, CLOCK) ( model dfscr (SCAN, RESET, QBAR, Q, DATA1, DATA, CLOCK) ( model dffsr (SET, RESET, QBAR, Q, DATA, CLOCK) ( model dfscsr (SET, SCAN, RESET, QBAR, Q, DATA1, DATA0, CLOCK) ( model inv1 (OUT, IN1) ( model nd2x1 (OUT, IN2, IN1) ( model nd4 (OUT, IN4, IN3, IN2, IN1) ( model ndi2x1 (OUT2, OUT1, IN2, IN1) ( model nr3 (OUT, IN3, IN2, IN1) ( model xor (OUT, IN2, IN1) (

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