Combinational ATPG Tutorial

Marufa Kaniz, Matthew Cole, Samiha Mourad


Date of last revision: 19/09/97


  1. Invoking Fastscan
  2. Generating the Test Patterns
  3. Viewing and Saving the Results




1. Invoking Fastscan

This tutorial gives us an overview of how to use combinational ATPG to generate test patterns for a combination circuit without using any scan based design. The program used for this is Fastscan. For this tutorial, we will use a schematic of a mux and the test library given at the end of this page.

  1. Copy the following files to that directory by entering the shell command:

    shell > cp -R /applications/webserver/docs/mentortu/mux .

  2. Copy the attributes file by entering the following shell command.

    shell> cp /applications/webserver/docs/mentortu/mux.mgc_component.attr .
  3. Make sure that you are in the same directory that you plan to execute fastscan from. Cut and paste the test library given at the end of the page into a text editor and save it as atglib

  4. Set the mentor graphics working directory to point to the directory that you plan to execute fastscan from. Type in the following command at the shell prompt.

    $ MGC_WD=`pwd`

    Note: Apostrophies surround pwd and not single quotes


  5. Invoke Fastscan as a graphical interface using a schematic by entering the following command from the shell prompt:

    $ fastscan mux -eddm -lib atglib


    After the command has completed execution, you should see the graphical interface shown below in Figure 1.



Figure 1

  1. From the main menu bar, select OPEN SHEET. The schematic should display in the window as shown in Figure 2.





Figure 2


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Test Library


model anotb (OUT, B, A) (

model aorbn (OUT, B, A) (

model dff (QBAR, Q, DATA, CLOCK) (

model dfsc (SCAN, QBAR, Q, DATA1, DATA, CLOCK) (

model dffr (RESET, QBAR, Q, DATA, CLOCK) (

model dfscr (SCAN, RESET, QBAR, Q, DATA1, DATA, CLOCK) (

model dffsr (SET, RESET, QBAR, Q, DATA, CLOCK) (

model dfscsr (SET, SCAN, RESET, QBAR, Q, DATA1, DATA0, CLOCK) (

model inv1 (OUT, IN1) (

model nd2x1 (OUT, IN2, IN1) (

model nd4 (OUT, IN4, IN3, IN2, IN1) (

model ndi2x1 (OUT2, OUT1, IN2, IN1) (

model nr3 (OUT, IN3, IN2, IN1) (

model xor (OUT, IN2, IN1) (