At the Design Center, School of Engineering, of Santa Clara University, we have developed a set of tutorials to help our students use Mentor Graphics Tools. The relationships of these tools to digital circuit design are outlined in the flowchart shown below.

No previous knowledge of CAD tools is needed to use these tutorials. However, they assumed that the users know their logic or circuit design principles. We explained how you start design entry from scratch. No "canned" design are required to download. We illustrated the use of Autologic with a very simple circuit that we included in the tutorial.

The tutorials have been used in undergraduate and graduate courses. We keep updating them as time permits and we look forward to your comments to improve them. Some of them are more mature than others. For example, we are updating QVHDL to include some testbench. Also, we have developed tutorials for Quickfault , ATPG for combinational and sequencial as well DFTAdvisor for Full Scan and Partial Scan. We plan to include them soon this Fall.

Acknowledgement: We wish to thank many people who have been supportive of and instrumental in developing these tutorials: Mentor Graphics Educational Gifts Program under the leadership of Julie Schroeder and with the support of Sue Drouin, Debbie Semperboni and Barry Carpenter; Boyd Donckels and Doug Lyons of Mentor Graphics at San Jose, who recognized the need of the tutorials not only for university teaching but also for all first time users of the tools; Rick Saunders and John O'Callaghan, of SCU Design Center, who have been instrumental in the installation and upgrade of the tools; LSI Logic, Quicklogic and Xilinx who have donated their tools; Matt Cole, Savitha Gandikota, Marufa Kaniz, and Sylvia Liu who actually developed the tutorials; and the many students who have used these tutorials in their class work and have providedus feedback.

• For logic design, start with either Design Architect or QuickVHDL and simulate using QuickSim
• Use the Autologic to synthesize your VHDL (or Verilog) design
• First draft for tutorials for Fault Simulation and Scan Insertion are also avaiable
• You may then map it into standard cells layout as explained in AutoCell
• The Accusim.tutorial instructs you how to enter and simulate a transistor level circuit design
• You may also use UC. Berkeley Spice 3f5.
• For full custom layout design, use IC Graph
• Use ICVerify to check and extract delay information from layout for re-simulation
• Included also are tutorials for both Xilinx and Quicklogic
• For the later FPGA , you are shown how to start from a schematic or VHDL description.

Note: Procedures not explained in tutorial can be found in Bookcase using Bold Browser -- which can be activated by selecting from main menu bar (after invoking tool):

Help -> on Bookcase

If you have any suggestions, please e-mail to smourad@scu.edu

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